-Independently take the design/verification tasks, such as DUT design,UVM/VMM/SV testbench debugging, and help other junior engineers to grow up. -Need to understand standard specifications/functional specifications/ feature enhancements for the product and create micro-architecture and detailed verification/design documents for some of the components of small complexity modules in the Test Environment for the DesignWare digital product, mainly such as USB4/USB3.2/USB3.1/USB3.0. -Create deliverables which do not depend on close review or supervision by a Senior Technical Lead. -May learn to do technical review of TE Code of small complexity. -The candidate should be able to analyze the code and function coverage metrics and improve them with definition of additional test cases in CRV environment, at least for small/ medium complexity features of the protocol/ product specs. -The candidate will work in a project and team oriented environment with teams spread across multiple sites, worldwide. -Must have BSEE in EE with 7+ years of relevant experience or MSEE with 6+ years of relevant experience in the following areas: -Design/Verification of IP Cores or SoC Designs for Set Top Boxes, Mobile handsets, Smart Devices, etc. -Knowledge of one or more of protocols: Ethernet/USB/AMBA/DP/PCIe -Hands on experience with creating detailed design of certain simple components of Test Environment from Functional Specifications/ Test Environment Specifications. The TE must have used methodologies such as UVM/ VMM. -Hands on experience with Verilog/SystemVerilog/ VERA coding and Simulation tools; Knowledge of CDC/C++/ OOPs Concepts -Experience with Perforce or similar revision control environment Knowledge of Makefile/Perl/Shell scripts.

武汉江夏区武汉未来科技城A