“Strong” and “weak” hardware memory models – Sutter’s Mill

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“Strong” and “weak” hardware memory models – Sutter’s Mill

2023-05-07 17:29| 来源: 网络整理| 查看: 265

@Jon: This was the terminology we used during the C++ and C memory model discussions (and Java, which I wasn’t involved with but did involve many of the same people): We talked about x86 as the poster child for strong because it has the strongest guarantees of mainstream hardware (not all of which guarantees are necessary or desirable, as I’ll mention in my talk on Tuesday) and especially it efficiently supports SC program semantics, whereas ARM(v7) and POWER require heavy sync operations to get SC program semantics. I say “SC program semantics” because it’s not only about atomics, though that is part of it.

Of course, no mainstream hardware is truly SC any more and will never be again, so “pure SC hardware” is of historical interest only. However, giving programs SC semantics is a very strong guarantee, even with the C++11/C11/Java qualifier “if you don’t write races,” and it’s important because it’s the only thing that anyone has been able to show mainstream developers can reason about successfully.

@Dave: Synchronizing using mutexes/cvs is what we prefer to teach people to use by default. Programming using SC atomics is indeed experts-only difficulty, but unfortunately it’s also justified more often than I would like (e.g., DCL, reference counting, and several other common patterns some of which should be wrapped in types but can’t always be) and so it turns out that we still have to teach SC atomics techniques to advanced-but-mainstream C++ programmers. However, programming using weaker-than-SC atomics is yet another major level of difficulty beyond that, and I don’t know if there are 100 people in the world who can reliably use those directly; I’m still trying to discourage resorting to them, although there currently are performance reasons to reach for them on ARMv7 and POWER. There is a difference of opinion among experts as to whether weaker-than-SC atomics are fully going away or not (e.g., they are lingering in 1000+ core count supercomputing applications), but with ARMv8 in particular the industry momentum in mainstream processors is going in the direction of seeing the performance carrot shrinking and disappearing for resorting to weaker-than-SC models.



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