Problems 61712.20 Refer t |
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Problems 61712.20 Refer to the bipolar DAC circuit in Figure 12.16. Describehow you would adjust the output for a range of10 V to (10 V 2 LSB). Include values of variablecomponents. Calculate the resolution of this circuit.12.21 A 3-bit DAC has a reference voltage of 12 V and a transfercharacteristic summarized in Table 12.8. Plot the dataon a graph similar to those in Figures 12.18 through12.20. From the data in Table 12.8, determine the offseterror, gain error, and linearity error of the DAC, both in %of full scale and as a fraction of an LSB.12.23 A 3-bit DAC has a reference voltage of 4 V and a transfercharacteristic summarized in Table 12.10. Plot the data ona graph. From the data in the Table 12.10, determine theoffset error, gain error, and linearity error of the DAC,both in % of full scale and as a fraction of an LSB.Table 12.10 DAC Transfer Characteristicfor Problem 12.23Digital Code Analog Output (volts)DAC Transfer Characteristic000 0.000001 0.500Analog Output (volts)010 1.025011 1.525100 1.985000 0.5101 2.675001 2.0110 3.000010 3.5111 3.500011 5.0100 6.5101 8.0110 9.5Section 12.3 Analog-to-Digital Conversion111 11.0DAC Transfer Characteristic12.24 How many comparators are needed to construct an 8-bitflash converter? Sketch the circuit of this converter. (It isonly necessary to show a few of the comparators and indicatehow many there are.)12.25 Briefly explain the operation of a flash ADC. What is thepurpose of the priority encoder? Explain how the latchcan be used to synchronize the output to a particular samplingfrequency.12.26 Why do we choose a value of R/2 for the LSB resistor ofa flash ADC?12.27 An 8-bit successive approximation ADC has a referenceAnalog Output (volts)voltage of 16 V. Describe the conversion sequence forthe case where the analog input is 4.75 V. Summarize the0000010100110.0001.0362.0713.107steps in Table 12.11. (Refer to Example 12.11.)12.28 What is displayed on the seven-segment display in Figure12.49 when v analog 5.25 V? Assume that the referencevoltage is 12 V and that the display can show hex digits.100 4.14312.29 Describe the operation of each part of the successive approximationADC shown in Figure 12.49 when the analog101 5.179110 6.214input changes from 5.25 V to 8.0 V. What is the new111 7.250number displayed on the seven-segment display?Table 12.11 Table for Problem 16.23New Digital Analog v analog Comparator AccumulatedBit Value Equivalent v DAC ? Output Digital ValueQ 7Q 6Q 5Q 4Q 3Q 2Q 1Table 12.8for Problem 12.21Digital Code12.22 A 3-bit DAC has a reference voltage of 8 V and a transfercharacteristic summarized in Table 12.9. Plot the data ona graph. From the data in Table 12.9, determine the offseterror, gain error, linearity error, and differential nonlinearityof the DAC, both in % of full scale and as a fractionof an LSB.Table 12.9for Problem 12.22Digital Code 618 CHAPTER 12 • Interfacing Analog and Digital CircuitsFIGURE 12.49Problem 12.28Successive ApproximationADC and Seven-SegmentDisplay12.30 a. An 8-bit successive approximation ADC has a referencevoltage of 12 V. Calculate the resolution of thisADC.b. The analog input voltage to the ADC in part a is 8 V.Can this input voltage be represented exactly? Whatdigital code represents the closest value to 8 V? Whatexact analog value does this represent? Calculate thepercent error of this conversion.12.31 What is the maximum quantization error of an ADC, relativeto a fraction of 1 LSB?12.32 An 8-bit dual slope analog-to-digital converter has a referencevoltage of 16 V. The integrator component valuesare: R 80 k, C 0.1 F. The analog input voltageis 14 V.Calculate the slope of the integrator voltage during:a. the integrating phase, andb. the rezeroing phase.c. How much time elapses during the rezeroing phase?(Assume that (1) the integrating and rezeroingtime are equal if the integrator output is at full scale,and (2) the reference voltage will rezero the integratorfrom full scale in exactly one counter cycle.)d. Sketch the integrator output waveform.e. What digital code is contained in the output latch afterthe conversion is complete?12.33 Repeat Problem 12.32 if the analog input voltage is 3 V.12.34 Repeat Problem 12.32 if the analog input voltage is 18 V.12.35 make a sketch of a basic sample and hold circuit andbriefly explain its operation.12.36 Explain why a sample and hold circuit may be needed atthe input of an analog-to-digital converter.12.37 What is the highest-frequency component of an analogsignal that can be accurately represented digitally if it issampled at a rate of 100 kHz?12.38 Calculate the minimum sampling frequency required topreserve all information when sampling a sine wave witha frequency of 130 kHz.12.39 Suppose a sine wave with a period of 4.8 s is sampledevery 5.2 s. What alias frequency will result? (Hint: seeFigure 12.33.)12.40 Calculate the corner frequency of an anti-aliasing filter foran ADC with a sampling frequency of 8 kHz. What type offilter (low-pass, high-pass, bandpass, etc.) is required?Section 12.4 Data Acquisition12.41 Refer to the data acquisition system in Figure 12.38.Write a VHDL file to implement the continuous-convertversion of the ADC controller, as represented in the statediagram of Figure 12.42. Create a simulation inMAXPLUS II to verify the operation of the controller.12.42 Use the state machine controller from Problem 12.41 and anoctal latch as components in a VHDL hierarchy that representsthe ADC interface of Figure 12.38. Create a simulationin MAXPLUS II to verify the operation of the design.12.43 The data acquisition system in Figure 12.38 is designedwith the controller from Problem 12.41. (The controllerstate diagram is shown in Figure 12.42.) Assume the controllerand latch are interfaced with a different ADC thathas a conversion time of 16 s, which is equivalent to 64clock cycles. Calculate the highest-frequency componentthat can be accurately converted with this system for aclock rate of 787 kHz.12.44 Repeat Problem 12.43 for a 4-channel data acquisitionsystem, assuming the same conversion rate for the ADCand the controller state diagram of Figure 12.45. Page 2 and 3:CHAPTER1❘❙❚❘❙❚❘❙❚ Page 4 and 5:1.2 • Digital Logic Levels 3FIGUR Page 6 and 7:1.3 • The Binary Number System 5t Page 8 and 9:1.3 • The Binary Number System 7S Page 10 and 11:1.3 • The Binary Number System 9 Page 12 and 13:1.3 • The Binary Number System 11 Page 14 and 15:1.4 • Hexadecimal Numbers 13❘ Page 16 and 17:1.5 • Digital Waveforms 15❘❙ Page 18 and 19:1.5 • Digital Waveforms 17Figure Page 20 and 21:1.5 • Digital Waveforms 19of the Page 22 and 23:Problems 21Continuous Smoothly conn Page 24:Answers To Section Review Problems Page 27 and 28:26 CHAPTER 2 • Logic Functions an Page 29 and 30:28 CHAPTER 2 • Logic Functions an Page 31 and 32:30 CHAPTER 2 • Logic Functions an Page 33 and 34:32 CHAPTER 2 • Logic Functions an Page 35 and 36:34 CHAPTER 2 • Logic Functions an Page 37 and 38:36 CHAPTER 2 • Logic Functions an Page 39 and 40:38 CHAPTER 2 • Logic Functions an Page 41 and 42:40 CHAPTER 2 • Logic Functions an Page 43 and 44:42 CHAPTER 2 • Logic Functions an Page 45 and 46:44 CHAPTER 2 • Logic Functions an Page 47 and 48:46 CHAPTER 2 • Logic Functions an Page 49 and 50:48 CHAPTER 2 • Logic Functions an Page 51 and 52:50 CHAPTER 2 • Logic Functions an Page 53 and 54:52 CHAPTER 2 • Logic Functions an Page 55 and 56:54 CHAPTER 2 • Logic Functions an Page 58 and 59:CHAPTER3❘❙❚❘❙❚❘❙❚ Page 60 and 61:3.1 • Boolean Expressions, Logic Page 62 and 63:3.1 • Boolean Expressions, Logic Page 64 and 65:3.1 • Boolean Expressions, Logic Page 66 and 67:3.1 • Boolean Expressions, Logic Page 68 and 69:3.2 • Sum-of-Products and Product Page 70 and 71:3.2 • Sum-of-Products and Product Page 72 and 73:3.2 • Sum-of-Products and Product Page 74 and 75:3.3 • Theorems of Boolean Algebra Page 76 and 77:3.3 • Theorems of Boolean Algebra Page 78 and 79:3.3 • Theorems of Boolean Algebra Page 80 and 81:3.3 • Theorems of Boolean Algebra Page 82 and 83:3.3 • Theorems of Boolean Algebra Page 84 and 85:3.3 • Theorems of Boolean Algebra Page 86 and 87:19. x x DeMorgan’s Theorems3.3 Page 88 and 89:3.4 • Simplifying SOP and POS Exp Page 90 and 91:3.4 • Simplifying SOP and POS Exp Page 92 and 93:3.5 • Simplification by the Karna Page 94 and 95:3.5 • Simplification by the Karna Page 96 and 97:3.5 • Simplification by the Karna Page 98 and 99:3.5 • Simplification by the Karna Page 100 and 101:3.5 • Simplification by the Karna Page 102 and 103:3.5 • Simplification by the Karna Page 104 and 105:3.5 • Simplification by the Karna Page 106 and 107:Glossary 105For example, addition i Page 108 and 109:Problems 107bubble-to-bubble conven Page 110 and 111:Problems 1093.15 Write the POS form Page 112 and 113:Problems 1113.30 Use the rules of B Page 114 and 115:Problems 113A B C D Y0 0 0 0 10 0 0 Page 116 and 117:CHAPTER4❘❙❚❘❙❚❘❙❚ Page 118 and 119:4.1 • What Is a PLD? 117Let’s l Page 120 and 121:4.2 • Programming PLDs Using MAX+ Page 122 and 123:4.3 • Graphic Design File 121In p Page 124 and 125:4.3 • Graphic Design File 123FIGU Page 126 and 127:4.3 • Graphic Design File 125FIGU Page 128 and 129:4.4 • Compiling MAX+PLUS II Files Page 130 and 131:4.5 • Hierarchial Design 129FIGUR Page 132 and 133:4.5 • Hierarchical Design 131FIGU Page 134 and 135:4.6 • Text Design File (VHDL) 133 Page 136 and 137:4.6 • Text Design File (VHDL) 135 Page 138 and 139:4.6 • Text Design File (VHDL) 137 Page 140 and 141:4.6 • Text Design File (VHDL) 139 Page 142 and 143:4.7 • Creating a Physical Design Page 144 and 145:4.7 • Creating a Physical Design Page 146 and 147:4.7 • Creating a Physical Design Page 148 and 149:4.7 • Creating a Physical Design Page 150 and 151:Glossary 149ote\maj_vote.sof. Click Page 152 and 153:Problems 151JTAG Chain Multiple JTA Page 154:Problems 153formation after the pow Page 157 and 158:156 CHAPTER 5 • Combinational Log Page 159 and 160:158 CHAPTER 5 • Combinational Log Page 161 and 162:160 CHAPTER 5 • Combinational Log Page 163 and 164:162 CHAPTER 5 • Combinational Log Page 165 and 166:164 CHAPTER 5 • Combinational Log Page 167 and 168:166 CHAPTER 5 • Combinational Log Page 169 and 170:168 CHAPTER 5 • Combinational Log Page 171 and 172:170 CHAPTER 5 • Combinational Log Page 173 and 174:172 CHAPTER 5 • Combinational Log Page 175 and 176:174 CHAPTER 5 • Combinational Log Page 177 and 178:176 CHAPTER 5 • Combinational Log Page 179 and 180:178 CHAPTER 5 • Combinational Log Page 181 and 182:180 CHAPTER 5 • Combinational Log Page 183 and 184:182 CHAPTER 5 • Combinational Log Page 185 and 186:184 CHAPTER 5 • Combinational Log Page 187 and 188:186 CHAPTER 5 • Combinational Log Page 189 and 190:188 CHAPTER 5 • Combinational Log Page 191 and 192:190 CHAPTER 5 • Combinational Log Page 193 and 194:192 CHAPTER 5 • Combinational Log Page 195 and 196:194 CHAPTER 5 • Combinational Log Page 197 and 198:196 CHAPTER 5 • Combinational Log Page 199 and 200:S 1D198 CHAPTER 5 • Combinational Page 201 and 202:200 CHAPTER 5 • Combinational Log Page 203 and 204:202 CHAPTER 5 • Combinational Log Page 205 and 206:204 CHAPTER 5 • Combinational Log Page 207 and 208:206 CHAPTER 5 • Combinational Log Page 209 and 210:208 CHAPTER 5 • Combinational Log Page 211 and 212:210 CHAPTER 5 • Combinational Log Page 213 and 214:212 CHAPTER 5 • Combinational Log Page 215 and 216:214 CHAPTER 5 • Combinational Log Page 217 and 218:216 CHAPTER 5 • Combinational Log Page 219 and 220:218 CHAPTER 5 • Combinational Log Page 222 and 223:CHAPTER6❘❙❚❘❙❚❘❙❚ Page 224 and 225:6.1 • Digital Arithmetic 223Sum b Page 226 and 227:6.2 • Representing Signed Binary Page 228 and 229:6.3 • Signed Binary Arithmetic 22 Page 230 and 231:6.3 • Signed Binary Arithmetic 22 Page 232 and 233:6.3 • Signed Binary Arithmetic 23 Page 234 and 235:6.4 • Hexadecimal Arithmetic 233M Page 236 and 237:6.5 • Numeric and Alphanumeric Co Page 238 and 239:6.5 • Numeric and Alphanumeric Co Page 240 and 241:6.6 • Binary Adders and Subtracto Page 242 and 243:6.6 • Binary Adders and Subtracto Page 244 and 245:6.6 • Binary Adders and Subtracto Page 246 and 247:6.6 • Binary Adders and Subtracto Page 248 and 249:6.6 • Binary Adders and Subtracto Page 250 and 251:6.6 • Binary Adders and Subtracto Page 252 and 253:6.6 • Binary Adders and Subtracto Page 254 and 255:6.6 • Binary Adders and Subtracto Page 256 and 257:6.6 • Binary Adders and Subtracto Page 258 and 259:6.6 • Binary Adders and Subtracto Page 260 and 261:6.7 • BCD Adders 259❘❙❚ SEC Page 262 and 263:6.7 • BCD Adders 261C 4 4 3 C 4 Page 264 and 265:6.8 • Carry Generation in MAXPLUS Page 266 and 267:6.8 • Carry Generation in MAXPLUS Page 268 and 269:Summary 267❘❙❚❘❙❚❘❙ Page 270 and 271:Glossary 269GLOSSARY1’s complemen Page 272 and 273:Problems 2716.10 Subtract the follo Page 274:Answers to Section Review Problems Page 277 and 278:276 CHAPTER 7 • Introduction to S Page 279 and 280:278 CHAPTER 7 • Introduction to S Page 281 and 282:280 CHAPTER 7 • Introduction to S Page 283 and 284:282 CHAPTER 7 • Introduction to S Page 285 and 286:284 CHAPTER 7 • Introduction to S Page 287 and 288:286 CHAPTER 7 • Introduction to S Page 289 and 290:288 CHAPTER 7 • Introduction to S Page 291 and 292:290 CHAPTER 7 • Introduction to S Page 293 and 294:292 CHAPTER 7 • Introduction to S Page 295 and 296:294 CHAPTER 7 • Introduction to S Page 297 and 298:296 CHAPTER 7 • Introduction to S Page 299 and 300:298 CHAPTER 7 • Introduction to S Page 301 and 302:300 CHAPTER 7 • Introduction to S Page 303 and 304:302 CHAPTER 7 • Introduction to S Page 305 and 306:304 CHAPTER 7 • Introduction to S Page 307 and 308:306 CHAPTER 7 • Introduction to S Page 309 and 310:308 CHAPTER 7 • Introduction to S Page 311 and 312:310 CHAPTER 7 • Introduction to S Page 313 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354 and 355:8.6 • MAX7000S CPLD 353The main s Page 356 and 357:8.7 • FLEX10K CPLD 355Table 8.2 T Page 358 and 359:8.7 • FLEX10K CPLD 357FIGURE 8.25 Page 360 and 361:Summary 359Embedded Array Block (EA Page 362 and 363:Problems 361In-system programmabili Page 364 and 365:CHAPTER9❘❙❚❘❙❚❘❙❚ Page 366 and 367:9.1 • Basic Concepts of Digital C Page 368 and 369:9.1 • Basic Concepts of Digital C Page 370 and 371:9.2 • Synchronous Counters 369Tab Page 372 and 373:9.2 • Synchronous Counters 371VCC Page 374 and 375:9.2 • Synchronous Counters 373K 0 Page 376 and 377:9.2 • Synchronous Counters 375The Page 378 and 379:9.3 • Design of Synchronous Count Page 380 and 381:FIGURE 9.15K-Map Simplification of Page 382 and 383:9.3 • Design of Synchronous Count Page 384 and 385:9.3 • Design of Synchronous Count Page 386 and 387:9.4 • Programming Binary Counters Page 388 and 389:9.4 • Programming Binary Counters Page 390 and 391:9.5 • Control Options for Synchro Page 392 and 393:9.5 • Control Options for Synchro Page 394 and 395:9.5 • Control Options for Synchro Page 396 and 397:9.5 • Control Options for Synchro Page 398 and 399:9.5 • Control Options for Synchro Page 400 and 401:9.5 • Control Options for Synchro Page 402 and 403:9.5 • Control Options for Synchro Page 404 and 405:9.6 • Programming Presettable and Page 406 and 407:9.6 • Programming Presettable and Page 408 and 409:9.6 • Programming Presettable and Page 410 and 411:9.6 • Programming Presettable and Page 412 and 413:9.6 • Programming Presettable and Page 414 and 415:9.7 • Shift Registers 4139.7 Shif Page 416 and 417:9.7 • Shift Registers 415FIGURE 9 Page 418 and 419:9.7 • Shift Registers 4171, above Page 420 and 421:9.7 • Shift Registers 419Data in0 Page 422 and 423:9.7 • Shift Registers 421AND2OR2O Page 424 and 425:9.7 • Shift Registers 423AND2OR2O Page 426 and 427:S 1INPUTNOTINPUTS 0NOTPINPUT0PINPUT Page 428 and 429:9.8 • Programming Shift Registers Page 430 and 431:9.8 • Programming Shift Registers Page 432 and 433:9.8 • Programming Shift Registers Page 434 and 435:9.8 • Programming Shift Registers Page 436 and 437:9.8 • Programming Shift Registers Page 438 and 439:9.8 • Programming Shift Registers Page 440 and 441:9.9 • Shift Register Counters 439 Page 442 and 443:9.9 • Shift Register Counters 441 Page 444 and 445:0 0 0 0Q 3 Q 2 Q 1 Q 0D Q D Q D Q D Page 446 and 447:9.9 • Shift Register Counters 445 Page 448 and 449:9.9 • Shift Register Counters 447 Page 450 and 451:Glossary 449e. Output decoding, whi Page 452 and 453:Problems 451CLKthe counter.)CTR DIV Page 454 and 455:Problems 453Table 9.20SequenceQ 3 Q Page 456 and 457:Problems 455FIGURE 9.91Problem 9.46 Page 458 and 459:CHAPTER10❘❙❚❘❙❚❘❙ Page 460 and 461:10.2 • State Machines with No Con Page 462 and 463:10.2 • State Machines with No Con Page 464 and 465:10.2 • State Machines with No Con Page 466 and 467:10.3 • State Machines with Contro Page 468 and 469:10.3 • State Machines with Contro Page 470 and 471:10.3 • State Machines with Contro Page 472 and 473:10.3 • State Machines with Contro Page 474 and 475:10.3 • State Machines with Contro Page 476 and 477:10.4 • Switch Debouncer for a Nor Page 478 and 479:10.4 • Switch Debouncer for a Nor Page 480 and 481:4792digit_1@682digit_1@792digit_1@5 Page 482 and 483:10.4 • Switch Debouncer for a Nor Page 484 and 485:4832digit@682digit@792digit@582digi Page 486 and 487:10.5 • Unused States in State Mac Page 488 and 489:in1INPUTclkINPUTq 2 q 1 q 0AND3d 2D Page 490 and 491:10.6 • Unused States in State Mac Page 492 and 493:Traffic Light Controller 491Figure Page 494 and 495:Problems 493Moore machine A state m Page 496 and 497:Problems 495a. In the idle state, t Page 498 and 499:CHAPTER11❘❙❚❘❙❚❘❙ Page 500 and 501:11.1 • Electrical Characteristics Page 502 and 503:11.1 • Electrical Characteristics Page 504 and 505:11.2 • Propagation Delay 503NOTEP Page 506 and 507:11.3 • Fanout 50511.3 FanoutKEY T Page 508 and 509:11.3 • Fanout 507Solution Since t Page 510 and 511:11.3 • Fanout 509www.electronicte Page 512 and 513:11.4 • Power Dissipation 511Power Page 514 and 515:11.4 • Power Dissipation 513Solut Page 516 and 517:11.5 • Noise Margin 515AAA 1 25 V Page 518 and 519:11.6 • Interfacing TTL and CMOS G Page 520 and 521:11.7 • Internal Circuitry of TTL Page 522 and 523:11.7 • Internal Circuitry of TTL Page 524 and 525:11.7 • Internal Circuitry of TTL Page 526 and 527:11.7 • Internal Circuitry of TTL Page 528 and 529:11.7 • Internal Circuitry of TTL Page 530 and 531:11.7 • Internal Circuitry of TTL Page 532 and 533:11.7 • Internal Circuitry of TTL Page 534 and 535:11.7 • Internal Circuitry of TTL Page 536 and 537:11.7 • Internal Circuitry of TTL Page 538 and 539:11.7 • Internal Circuitry of TTL Page 540 and 541:11.8 • Internal Circuitry of MOS Page 542 and 543:11.8 • Internal Circuitry of MOS Page 544 and 545:11.8 • Internal Circuitry of MOS Page 546 and 547:11.8 • Internal Circuitry of MOS Page 548 and 549:11.8 • Internal Circuitry of MOS Page 550 and 551:11.8 • Internal Circuitry of MOS Page 552 and 553:11.9 • TTL and CMOS Variations 55 Page 554 and 555:11.9 • TTL and CMOS Variations 55 Page 556 and 557:11.9 • TTL and CMOS Variations 55 Page 558 and 559:Summary 557Devices from earlier CMO Page 560 and 561:Glossary 559p-channel enhancement-m Page 562 and 563:Problems 561Section 11.4 Power Diss Page 564 and 565:Answers to Section Review Problems Page 566 and 567:CHAPTER12❘❙❚❘❙❚❘❙ Page 568 and 569: 12.1 • Analog and Digital SignalsPage 570 and 571: 12.1 • Analog and Digital SignalsPage 572 and 573: 12.2 • Digital-to-Analog ConversiPage 574 and 575: 12.2 • Digital-to-Analog ConversiPage 576 and 577: 12.2 • Digital-to-Analog ConversiPage 578 and 579: 12.2 • Digital-to-Analog ConversiPage 580 and 581: 12.2 • Digital-to-Analog ConversiPage 582 and 583: 12.2 • Digital-to-Analog ConversiPage 584 and 585: 12.2 • Digital-to-Analog ConversiPage 586 and 587: 12.2 • Digital-to-Analog ConversiPage 588 and 589: 12.2 • Digital-to-Analog ConversiPage 590 and 591: 12.2 • Digital-to-Analog ConversiPage 592 and 593: 12.3 • Analog-to-Digital ConversiPage 594 and 595: 12.3 • Analog-to-Digital ConversiPage 596 and 597: 12.3 • Analog-to-Digital ConversiPage 598 and 599: 12.3 • Analog-to-Digital ConversiPage 600 and 601: 12.3 • Analog-to-Digital ConversiPage 602 and 603: 12.3 • Analog-to-Digital ConversiPage 604 and 605: 12.3 • Analog-to-Digital ConversiPage 606 and 607: 12.4 • Data Acquisition 605Anti-aPage 608 and 609: 12.4 • Data Acquisition 607ADC080Page 610 and 611: 12.4 • Data Acquisition 609FIGUREPage 612 and 613: 12.4 • Data Acquisition 611Tfss=7Page 614 and 615: Summary 613FIGURE 12.46Simulation oPage 616 and 617: Problems 615GLOSSARYAliasing A phenPage 620: Answers 619ANSWERS TO SECTION REVIEPage 623 and 624: 622 CHAPTER 13 • Memory Devices aPage 625 and 626: 624 CHAPTER 13 • Memory Devices aPage 627 and 628: 626 CHAPTER 13 • Memory Devices aPage 629 and 630: 628 CHAPTER 13 • Memory Devices aPage 631 and 632: 630 CHAPTER 13 • Memory Devices aPage 633 and 634: 632 CHAPTER 13 • Memory Devices aPage 635 and 636: 634 CHAPTER 13 • Memory Devices aPage 637 and 638: 636 CHAPTER 13 • Memory Devices aPage 639 and 640: 638 CHAPTER 13 • Memory Devices aPage 641 and 642: 640 CHAPTER 13 • Memory Devices aPage 643 and 644: 642 CHAPTER 13 • Memory Devices aPage 645 and 646: 644 CHAPTER 13 • Memory Devices aPage 647 and 648: 646 CHAPTER 13 • Memory Devices aPage 649 and 650: 648 CHAPTER 13 • Memory Devices aPage 651 and 652: 650 CHAPTER 13 • Memory Devices aPage 653 and 654: 652 CHAPTER 13 • Memory Devices aPage 655 and 656: 654 CHAPTER 13 • Memory Devices aPage 658 and 659: APPENDIX AAltera UP-1 User Guide❘Page 660 and 661: APPENDIX A • Altera UP-1 User GuiPage 662 and 663: APPENDIX A • Altera UP-1 User GuiPage 664 and 665: APPENDIX A • Altera UP-1 User GuiPage 666 and 667: APPENDIX A • Altera UP-1 User GuiPage 668 and 669:APPENDIX A • Altera UP-1 User Gui Page 670 and 671:APPENDIX A • Altera UP-1 User Gui Page 672 and 673:APPENDIX A • Altera UP-1 User Gui Page 674 and 675:APPENDIX A • Altera UP-1 User Gui Page 676 and 677:APPENDIX A • Altera UP-1 User Gui Page 678 and 679:APPENDIX A • Altera UP-1 User Gui Page 680 and 681:APPENDIX A • Altera UP-1 User Gui Page 682 and 683:APPENDIX A • Altera UP-1 User Gui Page 684 and 685:APPENDIX A • Altera UP-1 User Gui Page 686 and 687:APPENDIX A • Altera UP-1 User Gui Page 688 and 689:APPENDIX A • Altera UP-1 User Gui Page 690 and 691:APPENDIX B❘❙❚❘❙❚❘❙ Page 692 and 693:APPENDIX B • VHDL Language Refere Page 694 and 695:APPENDIX B • VHDL Language Refere Page 696 and 697:APPENDIX B • VHDL Language Refere Page 698 and 699:APPENDIX B • VHDL Language Refere Page 700 and 701:APPENDIX B • VHDL Language Refere Page 702:APPENDIX B • VHDL Language Refere Page 705 and 706:APPENDIX C • Manufacturers’ Dat Page 707 and 708:APPENDIX C • Manufacturers’ Dat Page 709 and 710:APPENDIX C • Manufacturers’ Dat Page 711 and 712:APPENDIX C • Manufacturers’ Dat Page 713 and 714:APPENDIX C • Manufacturers’ Dat Page 715 and 716:APPENDIX C • Manufacturers’ Dat Page 717 and 718:APPENDIX C • Manufacturers’ Dat Page 719 and 720:APPENDIX C • Manufacturers’ Dat Page 721 and 722:APPENDIX C • Manufacturers’ Dat Page 723 and 724:APPENDIX C • Manufacturers’ Dat Page 725 and 726:APPENDIX C • Manufacturers’ Dat Page 727 and 728:APPENDIX C • Manufacturers’ Dat Page 729 and 730:APPENDIX C • Manufacturers’ Dat Page 731 and 732:APPENDIX C • Manufacturers’ Dat Page 733 and 734:APPENDIX C • Manufacturers’ Dat Page 735 and 736:APPENDIX C • Manufacturers’ Dat Page 737 and 738:APPENDIX C • Manufacturers’ Dat Page 739 and 740:APPENDIX C • Manufacturers’ Dat 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