Characteristics | Logic Gates | Counters | Decoders | Display drivers

Also see: 74 Series | ICs

There are many ICs in the 4000 series and this page only covers a selection, concentrating on the most useful gates, counters, decoders and display drivers. For each IC there is a diagram showing the pin arrangement and brief notes explain the function of the pins where necessary. The notes also explain if the IC's properties differ substantially from the standard characteristics listed below.

Rapid Electronics: 4000 series ICs

If you are using another reference please be aware that there is some variation in the terms used to describe input pins. I have tried to be logically consistent so the term I have used describes the pin's function when high (true). For example 'disable clock' on the 4026 is often labelled 'clock enable' but this can be confusing because it enables the clock when low (false). An input described as 'active low' is like this, it performs its function when low. If you see a line drawn above a label it means it is active low, for example:   (say 'reset-bar').

Recommended book: CMOS Cookbook

The Links page lists Datasheet websites.

The CMOS circuitry means that 4000 series ICs are static sensitive. Touching a pin while charged with static electricity (from your clothes for example) may damage the IC!

In fact most ICs in regular use are quite tolerant and earthing your hands by touching a metal water pipe or window frame before handling them will be adequate.

ICs should be left in their protective packaging until you are ready to use them.

It is best to build a circuit using just one logic family, but if necessary the different families may be mixed providing the power supply is suitable for all of them. For example mixing 4000 and 74HC requires the power supply to be in the range 3 to 6V. A circuit which includes 74LS or 74HCT ICs must have a 5V supply.

A 74LS output cannot reliably drive a 4000 or 74HC input unless a 'pull-up' resistor of 2.2k is connected between the +5V supply and the input to correct the slightly different logic voltage ranges used.

Note that a 4000 series output can drive only one 74LS input.

For tables showing characteristics of the logic families see: Logic ICs

Driving 4000 or 74HC inputs from a74LS output using a pull-up resistor.

The 4093 has Schmitt trigger inputs to provide good noise immunity. They are ideal for slowly changing or noisy signals. The hysteresis is about 0.5V with a 4.5V supply and almost 2V with a 9V supply.

Notice how gate 1 is spread across the two ends of the package.

NC = No Connection (unused pin).

This gate has a propagation time which is about 10 times longer than normal so it is not suitable for high speed circuits.

NC = No Connection (unused pin).

* = The AND output (pin 1) is not available on some versions of the 4068.

Inputs: These ICs are unusual because their gate inputs can withstand up to +15V even if the power supply is a lower voltage.

Outputs: These ICs are unusual because they are capable of driving 74LS gate inputs directly. To do this they must have a +5V supply (74LS supply voltage). The gate output is sufficient to drive four 74LS inputs.

NC = No Connection (unused pin).

Note the unusual arrangement of the power supply pins for these ICs!

Two 3-input NOR gates and a single NOT gate in one package.

NC = No Connection (unused pin).

The count advances as the clock input becomes high (on the rising-edge). Each output Q0-Q9 goes high in turn as counting advances. For some functions (such as flash sequences) outputs may be combined using diodes.

The reset input should be low (0V) for normal operation (counting 0-9). When high it resets the count to zero (Q0 high). This can be done manually with a switch between reset and +Vs and a 10k resistor between reset and 0V. Counting to less than 9 is achieved by connecting the relevant output (Q0-Q9) to reset, for example to count 0,1,2,3 connect Q4 to reset.

The disable input should be low (0V) for normal operation. When high it disables counting so that clock pulses are ignored and the count is kept constant.

The ÷10 output is high for counts 0-4 and low for 5-9, so it provides an output at 1/10 of the clock frequency. It can be used to drive the clock input of another 4017 (to count the tens).

Example projects: Heart badge | Traffic Light | Dice | Lighthouse

The count advances as the clock input becomes high (on the rising-edge). The outputs a-g go high to light the appropriate segments of a common-cathode 7-segment display as the count advances. The maximum output current is about 1mA with a 4.5V supply and 4mA with a 9V supply. This is sufficient to directly drive many 7-segment LED displays. The table below shows the segment sequence in detail.

The reset input should be low (0V) for normal operation (counting 0-9). When high it resets the count to zero.

The disable clock input should be low (0V) for normal operation. When high it disables counting so that clock pulses are ignored and the count is kept constant.

The enable display input should be high (+Vs) for normal operation. When low it makes outputs a-g low, giving a blank display. The enable out follows this input but with a brief delay.

The ÷10 output (h in table) is high for counts 0-4 and low for 5-9, so it provides an output at 1/10 of the clock frequency. It can be used to drive the clock input of another 4026 to provide multi-digit counting.

The not 2 output is high unless the count is 2 when it goes low.

The 'Random' flasher project uses the 4026 in an unconventional way, the outputs a-g and the ÷10 output (h) are used to flash individual LEDs in a complex pattern which appears random if not studied too closely!

The 4029 is a synchronous counter so its outputs change precisely together on each clock pulse. This is helpful if you need to connect the outputs to logic gates because it avoids the glitches which occur with ripple counters.

The count occurs as the clock input becomes high (on the rising-edge). The up/down input determines the direction of counting: high for up, low for down. The state of up/down should be changed when the clock is high.

For normal operation (counting) preset, and carry in should be low.

The binary/decade input selects the type of counter: 4-bit binary (0-15) when high; decade (0-9) when low.

The counter may be preset by placing the desired binary number on the inputs A-D and briefly making the preset input high. There is no reset input, but preset can be used to reset the count to zero if inputs A-D are all low.

Please see below for details of connecting synchronous counters like the 4029 in a chain.

These are synchronous counters so their outputs change precisely together on each clock pulse. This is helpful if you need to connect their outputs to logic gates because it avoids the glitches which occur with ripple counters.

The count occurs as the clock input becomes high (on the rising-edge). The up/down input determines the direction of counting: high for up, low for down. The state of up/down should be changed when the clock is high.

For normal operation (counting) preset, reset and carry in should be low. When reset is high it resets the count to zero (0000, QA-QD low). The clock input should be low when resetting.

The counter may be preset by placing the desired binary number on the inputs A-D and briefly making the preset input high, the clock input should be low when this happens.

Please see below for details of connecting synchronous counters like the 4510 and 4516 in a chain.

The diagram below shows how to link synchronous counters. Notice how all the clock (CK) inputs are linked. Carry out (CO) feeds carry in (CI) of the next counter. Carry in (CI) of the first counter should be low for 4029, 4510 and 4516 counters.

These contain two separate synchronous counters, one on each side of the IC.

Normally a clock signal is connected to the clock input, with the enable input held high. Counting advances as the clock signal becomes high (on the rising-edge).

For normal operation the reset input should be low, making it high resets the counter to zero (0000, QA-QD low).

Counting to less than the maximum (9 or 15) can be achieved by connecting the appropriate output(s) to the reset input, using an AND gate if necessary. For example to count 0 to 8 connect QA (1) and QD (8) to reset using an AND gate.

Special arrangements are used to link 4518/20 counters in a chain, as explained below.

The diagram below shows how to link 4518 and 4520 counters. Notice how the normal clock inputs are held low, with the enable inputs being used instead. With this arrangement counting advances as the enable input becomes low (on the falling-edge) allowing output QD to supply a clock signal to the next counter. The complete chain is a ripple counter, although the individual counters are synchronous! If it is essential to have truly synchronous counting a system of logic gates is required, please see a 4518/20 datasheet for further details.

The 4020 is a ripple counter so beware that glitches may occur in any logic gate systems connected to its outputs due to the slight delay before the later counter outputs respond to a clock pulse.

The count advances as the clock input becomes low (on the falling-edge), this is indicated by the bar over the clock label. This is the usual clock behaviour of ripple counters and it means a counter output can directly drive the clock input of the next counter in a chain.

Output Qn is the nth stage of the counter, representing 2n, for example Q4 is 24 = 16 (1/16 of clock frequency) and Q14 is 214 = 16384 (1/16384 of clock frequency). Note that Q2 and Q3 are not available.

The reset input should be low for normal operation (counting). When high it resets the count to zero (all outputs low).

Also see: 4040 (12-bit) and 4060 (14-bit with internal oscillator).

The 4024 is a ripple counter so beware that glitches may occur in any logic gate systems connected to its outputs due to the slight delay before the later counter outputs respond to a clock pulse.

The count advances as the clock input becomes low (on the falling-edge), this is indicated by the bar over the clock label. This is the usual clock behaviour of ripple counters and it means a counter output can directly drive the clock input of the next counter in a chain.

Output Qn is the nth stage of the counter, representing 2n, for example Q4 is 24 = 16 (1/16 of clock frequency) and Q7 is 27 = 128 (1/128 of clock frequency).

The reset input should be low for normal operation (counting). When high it resets the count to zero (all outputs low).

The 4040 is a ripple counter so beware that glitches may occur in any logic gate systems connected to its outputs due to the slight delay before the later counter outputs respond to a clock pulse.

The count advances as the clock input becomes low (on the falling-edge), this is indicated by the bar over the clock label. This is the usual clock behaviour of ripple counters and it means a counter output can directly drive the clock input of the next counter in a chain.

Output Qn is the nth stage of the counter, representing 2n, for example Q4 is 24 = 16 (1/16 of clock frequency) and Q12 is 212 = 4096 (1/4096 of clock frequency).

The reset input should be low for normal operation (counting). When high it resets the count to zero (all outputs low).

Also see these 14-bit counters: 4020 and 4060 (includes internal oscillator).

The 4060 is a ripple counter so beware that glitches may occur in any logic gate systems connected to its outputs due to the slight delay before the later counter outputs respond to a clock pulse.

The count advances as the clock input becomes low (on the falling-edge), this is indicated by the bar over the clock label. This is the usual clock behaviour of ripple counters and it means a counter output can directly drive the clock input of the next counter in a chain. The clock can be driven directly, or connected to the internal oscillator (see below).

Output Qn is the nth stage of the counter, representing 2n, for example Q4 is 24 = 16 (1/16 of clock frequency) and Q14 is 214 = 16384 (1/16384 of clock frequency). Note that Q1-3 and Q11 are not available.

The reset input should be low for normal operation (counting). When high it resets the count to zero (all outputs low).

Example projects: Christmas Decoration | Valentine Heart

The 4060 includes an internal oscillator. The clock signal may be supplied in three ways:

Also see: 4020 (14-bit) and 4040 (12-bit), neither of these have internal oscillators.

The appropriate output Q0-9 becomes high in response to the BCD (binary coded decimal) input. For example an input of binary 0101 (=5) will make output Q5 high and all other outputs low.

The 4028 is a BCD (binary coded decimal) decoder intended for input values 0 to 9 (0000 to 1001 in binary). With inputs from 10 to 15 (1010 to 1111 in binary) all outputs are low.

Note that the 4028 can be used as a 1-of-8 decoder if input D is held low.

Also see: 4017 (a decade counter and 1-of-10 decoder in a single IC).

The appropriate outputs a-g become high to display the BCD (binary coded decimal) number supplied on inputs A-D. The outputs a-g can source up to 25mA. The 7-segment display segments must be connected between the outputs and 0V with a resistor in series (330 with a 5V supply). A common cathode display is required.

Display test and blank input are active-low so they should be high for normal operation. When display test is low all the display segments should light (showing number 8). When blank input is low the display is blank (all segments off).

The store input should be low for normal operation. When store is high the displayed number is stored internally to give a constant display regardless of any changes which may occur to the inputs A-D.

The 4511 is intended for BCD (binary coded decimal). Inputs values from 10 to 15 (1010 to 1111 in binary) will give a blank display (all segments off).

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