Study of slag 　 ༽: 感谢分享，学习了

Aaron_kosminski: 还ok

进化-evolution: 有用

chengqingting: [code=csharp] #include "def.h" #include "2410addr.h" #include "2410IIC.h" #include "board.h" #define Uart_Printf printf static U8 _iicData[IICBUFSIZE]; static volatile int _iicDataCount; static volatile int _iicStatus; static volatile int _iicMode; static int _iicPt; [/code]

chengqingting: [code=csharp] U8 SetSysFclk(U32 val) {U32 i, freq; U8 mdiv, pdiv, sdiv; if(SlowMode) return FALSE; // PLL Control Register (MPLLCON and UPLLCON) // Mpll = (m * Fin) / (p * 2的s次方) // m = (MDIV + 8), p = (PDIV + 2), s = SDIV // PLL Value Selection Guide // 1. Fout = m * Fin / (p*2^s), Fvco = m * Fin / p where : m=MDIV+8, p=PDIV+2, s=SDIV // 2. Fin/(25*p) < 28.449e6/m < Fin/(10*p) // 3. 0.7 < 3.373/sqrt(m) < 1.8 // 4. 160e6 £ Fvco £ 400e6 // 5. 20e6 £ Fout £ 300e6 ( The max. Fout of the PLL itself is 300Mhz ) // 6. FCLK ³ 3X-tal or 3EXTCLK mdiv = (val>>12)&0xff;//mdiv= pdiv = (val>>4)&0x3f;//pdiv= sdiv = val&0x3;//sdiv=p * 2的s次方 i = (pdiv+2); while(sdiv--) i *= 2; freq = ((mdiv+8)*EXT_XTAL_FREQ)/i; if(freq>=(3*EXT_XTAL_FREQ)) {rMPLLCON = val; SYS_FCLK = freq; SetHclkPclk(); if(os_timer_run) {os_timer_rld = SYS_PCLK/(8*4*Timer4Freq)-1; chg_os_timer = 1;} if(bios_timer_run) {bios_timer_rld = SYS_PCLK/(8*4*BIOS_TIMER_FREQ)-1; chg_bios_timer = 1;} return TRUE;} return FALSE;} [/code]