55 nm硅 |
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图 9 (a)闪存单元中MT的布局简图和沟道边缘的漏电路径; (b)沿虚线A—A', MT可等效成一个主晶体管与两个寄生晶体管的并联, MT靠近隔离氧化物处反型层的形成导致寄生电流产生 Fig. 9. (a) MT top view with the leakage paths at the channel edges; (b) cross-section of MT along line A–A' indicates that MT can be considered as a main transistor in parallel with two parasitic transistors. The formation of the inverse layer along the isolated oxide leads to the generation of parasitic currents. |
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