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主要功能要求：
1、电子时钟。要求用 24 时制显示。分屏显示“时、分”和“分、秒”，即 4 个数码管不能同时显示“时、分、秒”，但可以只显示“时、分”，或只显示“分、秒”，通过按键来切换这两种显示方式。用数码管的小数点“.”代替时、分、秒的分隔符“：”。可设置时间。设置时间时，当前设置的“时”/“分”，相应的数码管应闪烁。 2、秒表（计时器）。秒表精度为 0.01 秒，计时范围 0~99.99 秒，用 4 个数码管显示，两个显示秒，两个显示百分秒，有暂停/继续、重置（清零）按钮。 3、定时器。可以实现 0~9999 秒定时。设置一定时值，当计时到达设定值时输出 LED 闪烁。有设置、暂停/继续、清零定时按钮。
参考思路：
上电默认显示 “时.分”，依次按下 MOD 按钮，分别显示“分.秒”、“秒表”、“定时器”
显示 “时.分”时，按下“SET”按钮，最右边的数码管闪烁，表示对这个数设置，按下“”按键加 1，按该数的进制自动翻转；再按下“SET”按键，往左移一个位置的位进入设置状态（闪烁）；到达最左侧的数位后，又从最右边的数位开始，如此环。按下“OK”按键退出设置。
初次显示“秒表”时，显示“0000”，按下“↑”按钮，开始计时，再按一次“↑”则暂停，按下“CLR”按钮重置（清零）。
初次显示“定时器”时，显示“0000”，按下“SET”按钮，进入设置定时的时间，首次按下“SET”，最右边的数码管闪烁，表设置此数位，再按下“SET”按键，往左移一个位置的位进入设置状态（闪烁）；到达最左侧的数位后，又从最右边的数位开始，如此循环。按下“OK”按键退出设置。按下“↑”按钮，开始计时，再按一次“↑”则暂停，按下“CLR”结束计时（回到初次显示定时器的状态，即显示“0000”）。若定时到达设定值，停止计数并闪烁 LED。 以上方案共需：5 个按键： MOD、SET、↑、OK、CLR
硬件实物图：
1.顶层部分代码：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multifunction_electronic_clock is
port(
clk:in std_logic;
mode:in std_logic;
set:in std_logic;
step_up:in std_logic;
ok:in std_logic;
clr:in std_logic;
CS:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DIS:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
led:out std_logic
);
end entity;
architecture STRUCT of multifunction_electronic_clock is
component key is
port(
clk:in std_logic;
mode:in std_logic;
set:in std_logic;
step_up:in std_logic;
ok:in std_logic;
clr:in std_logic;
mode_out:out std_logic;
set_out:out std_logic;
step_up_out:out std_logic;
ok_out:out std_logic;
clr_out:out std_logic
);
end component;
COMPONENT FENPIN IS
PORT(
CLK:IN STD_LOGIC;
C0:buffer STD_LOGIC;--1hz
C1:buffer STD_LOGIC;--100khz
C2:buffer STD_LOGIC;--闪烁频率
C3:BUFfer STD_LOGIC --100hz
);
END COMPONENT;
component controller is
port(
clk:in std_logic;
mode:in std_logic;
set:in std_logic;
ok:in std_logic;
mode_out:out std_LOGIC_VECTOR(1 downto 0);
flag1,flag2:buffer std_logic_vector(2 downto 0)
);
end component;
component clock is
port(
clk1:in std_logic;
clk:in std_LOGIC;
flag1:in std_logic_vector(2 downto 0);
step_up:in std_LOGIC;
D_0,D_1:out std_logic_vector(3 downto 0);
D_2,D_3:out std_logic_vector(3 downto 0);
D_4,D_5:out std_logic_vector(3 downto 0)
);
end component;
component shining is
port(
mode:in std_logic_vector(1 downto 0);
clk1:in std_logic;
clk:in std_logic;
flag1,flag2:in std_logic_vector(2 downto 0);
D_2_IN,D_3_IN,D_4_IN,D_5_IN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D_10_IN,D_11_IN,D_12_IN,D_13_IN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D_2,D_3,D_4,D_5,D_10,D_11,D_12,D_13:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end component;
component selection is
port(
clk:in std_logic;
MODE:IN STD_logic_vector(1 DOWNTO 0);
D_0,D_1,D_2,D_3,D_4,D_5:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D_6,D_7,D_8,D_9:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D_10,D_11,D_12,D_13:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D_0_OUT,D_1_OUT,D_2_OUT,D_3_OUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end component;
component stopwatch is
port(
MODE:IN STD_logic_vector(1 DOWNTO 0);
CLK:IN STD_LOGIC;
START:IN STD_LOGIC;
CLR:IN STD_LOGIC;
D_6,D_7,D_8,D_9:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end component;
component timer is
port(
clk:in std_logic;
MODE:IN STD_logic_vector(1 DOWNTO 0);
CLK_1hz:IN STD_LOGIC;
clk_2hz:in std_logic;
flag2:in std_logic_vector(2 downto 0);
STEP_UP:IN STD_LOGIC;
START:IN STD_LOGIC;--OK键
CLR:IN STD_LOGIC;
D_10,D_11,D_12,D_13:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
LED:OUT STD_LOGIC
);
end component;
component seg7led is
PORT(
mode:in std_logic_vector(1 downto 0);
CLK4:IN STD_LOGIC;--时钟，复位信号
CLEAR:in std_logic;
D_0,D_1,D_2,D_3: IN STD_LOGIC_VECTOR(3 DOWNTO 0);--BCD码输入信号
CS:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);--数码管位选信号
DIS:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)--数码管编码信号
);
END COMPONENT;
SIGNAL mode_out,set_out,step_up_out,ok_out,clr_out:STD_LOGIC;
SIGNAL C_1hz,C_100khz,C_2hz,C_100hz,C_1000HZ:STD_LOGIC;
SIGNAL MODE_STATE:STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL FLAG1,FLAG2:std_logic_vector(2 downto 0);
SIGNAL D_CLOCK0,D_CLOCK1,D_CLOCK2,D_CLOCK3,D_CLOCK4,D_CLOCK5:STD_LOGIC_VECTOR(3
SIGNAL D_2,D_3,D_4,D_5,D_10,D_11,D_12,D_13:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL D_S0,D_S1,D_S2,D_S3:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL D_6,D_7,D_8,D_9:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL D_TIMER10,D_TIMER11,D_TIMER12,D_TIMER13:STD_LOGIC_VECTOR(3 DOWNTO 0);
begin
u1:key port map(clk,mode,set,step_up,ok,clr,mode_out,set_out,step_up_out,ok_out,clr_out);
u2:fenpin port map(clk,c_1hz,c_100khz,c_2hz,c_100hz);
u3:controller port map(clk,mode_out,set_out,ok_out,mode_state,flag1,flag2);
u4:clock port map(clk,c_1hz,flag1,step_up_out,D_CLOCK0,D_CLOCK1,D_CLOCK2,D_CLOCK3,D_CLOCK4,D_CLOCK5);
u5:shining port map(modE_STATE,clk,c_2hz,flag1,flag2,D_CLOCK2,D_CLOCK3,D_CLOCK4,D_CLOCK5,D_TIMER10,D_TIMER11,D_TIMER12,D_TIMER13,D_2,D_3,D_4,D_5,D_10,D_11,D_12,D_13);
u6:selection port map(clk,MODE_STATE,D_CLOCK0,D_CLOCK1,D_2,D_3,D_4,D_5,D_6,D_7,D_8,D_9,D_10,D_11,D_12,D_13,D_S0,D_S1,D_S2,D_S3);
u7:stopwatch port map(MODE_STATE,C_100hz,STEP_UP_OUT,clr_out,D_6,D_7,D_8,D_9);
u8:timer port map(clk,MODE_STATE,C_1hz,c_2hz,FLAG2,STEP_UP_OUT,OK_OUT,clr_out,D_TIMER10,D_TIMER11,D_TIMER12,D_TIMER13,LED);
u9:seg7led port map(MODE_STATE,C_100khz,clr_out,D_S0,D_S1,D_S2,D_S3,CS,DIS);
end strUCT;
2.按键代码
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_unsigned.all;
4
5 entity key is
6 port(
7 clk:in std_logic;-- 系 统 50MHz 率 来 频 进
8 mode,set,step_up,ok,clr:in std_logic;
9 mode_out,set_out,step_up_out,ok_out,clr_out:out std_logic
10 -- 当按 按下后 键 ， 出一个上升脉冲 输
11 );
12 end key;
13
14 architecture behav of key is
15 begin
16
17 PROCESS(CLK,mode,set,step_up,ok,clr)
18 VARIABLE COUNT1,COUNT2,COUNT3,COUNT4,COUNT5:INTEGER RANGE 0 TO 1000000; --20ms
19 BEGIN
20
21 IF RISING_EDGE(CLK) THEN
22 IF mode='0' THEN
23 IF COUNT1 |