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昨天在altera的一篇官方文档上看到一段程序，代码如下：
1: //Top-level module
2: module TEST_NO(A,B,Clock,Reset,Sel,AddSub,Z,Overflow);
3: parameter n=16;
4: input [n-1:0]A,B;
5: input Clock,Reset,Sel,AddSub;
6: output [n-1:0]Z;
7: output Overflow;
8: reg SelR,AddSubR,Overflow;
9: reg [n-1:0]Areg,Breg,Zreg;
10: wire [n-1:0]G,H,M,Z;
11: wire carryout,over_flow;
12:
13: //Define combinational logic circuit
14: assign H=Breg^{n{AddSubR}};
15: mux2to1 multiplexer(Areg,Z,SelR,G);
16: defparam multiplexer.k=n;
17:
18: adderk nbit_adder(AddSubR,G,H,M,carryout);
19: defparam nbit_adder.k=n;
20: assign over_flow=carryout^G[n-1]^H[n-1]^M[n-1];
21: assign Z=Zreg;
22:
23:
24: //Define flip-flops and registers
25: always @(posedge Reset or posedge Clock)
26: if(Reset==1)
27: begin
28: Areg |