Select input elements from vector, matrix, or multidimensional signal

Libraries: Simulink / Signal Routing HDL Coder / Signal Routing

The Selector block extracts selected elements of an input vector, matrix, or multidimensional signal based on specified indices. The extracted signals can be grouped differently than the input signals.

Based on the value you enter for the Number of input dimensions parameter, a table of indexing settings is displayed. Each row of the table corresponds to one of the input dimensions in Number of input dimensions. For each dimension, you define the elements of the signal to work with. Specify a vector signal as a 1-D signal and a matrix signal as a 2-D signal. When you configure the Selector block for multidimensional signal operations, the block icon changes.

For example, assume a 6-D signal with a one-based index mode. The table of the Selector block dialog changes to include one row for each dimension. If you define dimensions as shown in the next table, the output is Y = U(1:end,2:6,[1 3 5],Idx4:Idx4+7,Idx5,Idx6(1):Idx6(2)), where Idx4, Idx5, and Idx6 are the index ports for dimensions 4, 5, and 6.

You can use an array of buses as an input signal to a Selector block. For details about defining and using an array of buses, see Group Nonvirtual Buses in Arrays of Buses.

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This example shows two Selector blocks with the same kind of input signals, but two different Index Option settings.

Both Selector blocks select 7 values from the input signal that feeds the input port. The Selector1 block outputs a fixed-size signal, whereas the Selector2 block outputs a variable-size signal whose compiled signal dimension is 10 instead of 7.

The Selector1 block sets Index Option to Index vector (port), which uses the input signal from Constant1 as the index vector. The dimension of the input signal is 7, so the Display block shows the 7 values of the Constant1 block. The Selector2 block sets the Input port size parameter to 10, which is the size of the largest input signal to the Selector2 block.

The Selector2 block also sets the Index Option to Starting and ending indices (port). The output is then set to the size of Input port size parameter (10), even though the size of the input signal is 7.

Generate bounded variable-size signals and illustrates some of the operations using those signals. In this example, you generate variable-size signals using the Selector block and the Switch block. The signals are used in math operations, bus creation, bus selection matrix concatenation, and to implement a discrete filter equation.

Use different operation modes to correspond to different signal sizes.

Use arrays of buses to represent structured data compactly.

The Index parameter is not tunable during simulation. If the Index Option for a dimension is set to Index vector (dialog) or Starting index (dialog) and you specify a symbolic value, including a Simulink.Parameter object, for the corresponding Index in the block dialog, then the instantaneous value at the start of simulation will be used throughout the simulation, and the parameter will appear as an inlined value in the generated code. See Tune and Experiment with Block Parameter Values. You can adjust the selection index dynamically by using index ports.

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Input signal and source of elements to output signal.

Data Types: single | double | half | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated | bus | image

External port specifying an index for the selection of the corresponding output element.

You can specify integer of custom width (for example, a 15-bit integer or 23-bit integer) as an index signal value. When you configure the width of the integer, you must specify the Mode as Fixed point, with Word length less than or equal to 128, Slope equal to 1, and Bias equal to 0. For more information on specifying a fixed-point data type, see Specify Data Types Using Data Type Assistant.

To enable an external index port, in the corresponding row of the Index Option table, set Index Option to Index vector (port), Starting index (port), or Starting and ending indices (port).

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32

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Output signal generated from selected or reordered elements of input signal.

Data Types: single | double | half | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated | bus | image

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Specifies the number of dimensions of the input signal.

Specifies the indexing mode. If One-based is selected, an index of 1 specifies the first element of the input vector. If Zero-based is selected, an index of 0 specifies the first element of the input vector.

Defines, by dimension, how the elements of the signal are to be indexed. From the list, select:

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No further configuration is required. All elements are selected.

Index vector (dialog)

Enables the Index column. Enter the vector of indices of the elements.

Index vector (port)

No further configuration is required.

Starting index (dialog)

Enables the Index and Output Size columns. Enter the starting index of the range of elements to select in the Index column and the number of elements to select in the Output Size column.

Starting index (port)

Enables the Output Size column. Enter the number of elements to be selected in the Output Size column.

Starting and ending indices (port)

No further configuration is required.

Using this option results in a variable-size output signal. When you update, the output dimension is set to be the same as the input signal dimension. During execution, the output dimension is updated based on the signal feeding the index.

When logging output signal data, signals not selected are padded with NaN values.

The Index and Output Size columns appear as needed.

If the Index Option is Index vector (dialog), enter the index of each element you are interested in.

If the Index Option is Starting index (dialog), enter the starting index of the range of elements to be selected.

Specifies the width of the block output signal.

Specify the width of the block input signal for 1-D signals. Enter -1 to inherit from the driving block.

Specify the time interval between samples. To inherit the sample time, set this parameter to -1. For more information, see Specify Sample Time.

This parameter is visible only if you set it to a value other than -1. To learn more, see Blocks for Which Sample Time Is Not Recommended.

Select this check box to have Simulink® check during simulation in accelerator or rapid accelerator mode whether any index values are outside the range of valid indices for the relevant dimension of the input signal. If an index is out of range, Simulink stops the simulation and displays an error message.

Note

If you do not select this check box, out-of-range index values could lead to undefined behavior during accelerator or rapid accelerator mode simulation.

Simulink performs this check during normal mode simulation regardless of whether you select this check box.

Data Types

Boolean | double | enumerated | fixed point | half | integer | single

Direct Feedthrough

no

Multidimensional Signals

yes

Variable-Size Signals

yes

Zero-Crossing Detection

no

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

This block has one default HDL architecture.

Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).

Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).

Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Specify whether to map the blocks in your design to inherit, Max, Min, or Zero for the floating-point operator. The default is inherit. See also LatencyStrategy (HDL Coder).

This block supports code generation for complex signals.

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Starting in R2023a, you can customize the width of the integer that you use to specify the index signal value for the Selector block.

Starting in R2023a, a Selector block that is configured to accept a 1-D variable-size input signal, supports Index vector (dialog) and Starting index (dialog) as the Index Option.

This enhancement allows you to choose from all the available Index Option settings when you configure the Selector block to accept a1-D variable-size input signal.

Assignment | Switch | Bus Selector