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linux驱动移植
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一、CCF子系统概述
计算机硬件通过许多时钟设备提供时钟。从进入系统内部的 cpu core 时钟开始，使用数十种时钟，如 timer、i2c、uart 等。每个 ARM SoC都通过多个时钟设备驱动程序设置时钟，硬件千差万别。 linux内核采用了一个时钟子系统来解决这个问题。在linux 3.4之后的版本，linux内核时钟子系统又叫通用时钟框架子系统，简称CCF子系统(common clock framework)。 CCF子系统是用来管理系统clock资源的子系统，根据职能，可以分为三个部分： 向其它驱动提供操作clock的通用API，屏蔽其中的硬件特性； 实现clock控制的通用逻辑，这部分和硬件无关，向上提供统一的操作接口，向下提供底层platform操作的接口； 将和硬件相关的clock控制逻辑封装成操作函数集，交由底层的platform开发者实现；比如选择哪个时钟源，设置输出的频率等； 1.1 时钟种类说明在s3c2410时钟章节中我们曾经介绍了其复杂的时钟结构，下图是一个简单的clock结构图：
如上图所示，时钟大致可以分为如下几种： 提供基础时钟源的晶振(有源晶振、无源晶振)； 用于倍频的PLL(锁相环，Phase Locked Loop)； 用于分频的divider 用于多路选择的mux； 用于clock enable控制的与门； 各个时钟模块的组合；虽然每一个SOC的时钟控制器的寄存器地址空间和具体结构略有差异，但是时钟控制器的组成目前来说，基本都是这个样子。 在CCF子系统的抽象中，将这六种不同类型的时钟均抽象出来： 定义不同的结构体，比如struck clk_gate、struct clk_mux等，他们都是对struct clk_hw的封装；如果你学过OOP的话，可以把 clk_hw看到是时钟基类，而把clk_gate、clk_mux看做具体的子类； 提供了单独的时钟注册函数，比如clk_register_gate、clk_register_mux等，也就是对clk_register函数的封装体； 针对硬件时钟的操作接口，也抽象了对应的结构体struct clk_ops，包含时钟的使能接口、时钟频率的修改接口等等；在针对上述所说的不同种类的时钟，其并不需要实现所有struct clk_ops中定义的接口，如下图所示: 针对时钟使能的与门电路而言，仅需要实现enable、disable、is_enable接口即可; 针对多路时钟选择的mux而言，则需要实现父时钟的设置及获取的接口set_parent、get_parent等； 对于倍频、分频而言，则需要实现时钟频率相关的接口set_rate、recalc_rate等；
下图是CCF子系统的架构图，其对各设备驱动提供统一时钟操作的接口，实现为： 根据硬件设备名获取其对应的输入时钟： 配置时钟（使能时钟、时钟频率配置）；在CCF内部，针对每一个时钟，抽象基类结构为struct clk_hw，该结构体中包含每一个硬件时钟的操作接口struct clk_ops，当时钟驱动程序完成时钟操作接口的定义，并调用clk_register完成注册后，则CCF即可借助clk_hw的clk_ops完成对时钟的参数配置等操作。 在linux内核中称clock driver为clock provider，相应的clock的使用者一般也是我们设备驱动程序称为clock consumer。 二、CCF子系统基本数据结构CCF子系统抽象了数据结构struck clk、struct clk_hw、struct clk_ops： clk_hw是对一个时钟的抽象基类（具体的子类，根据时钟种类的不同定义不同，比如clk_gate、clk_mux，这里就不一一介绍了）； clk_ops是时钟的操作接口的抽象； struct clk：对于驱动开发来说，struct clk只是访问时钟的一个句柄，有了它，驱动开发就可以对时钟进行配置；其中sruct clk_hw结构包含了struck clk成员； 2.1 struct clk(drivers/clk/clk.c)一个系统的时钟树结构是固定的，因此时钟的数目和用途也是固定的，我们以上面我们的案例图为例，假设其为一个完整的时钟系统，它的时钟包括：osc_clk、pll1_clk、pll2_clk、pll3_clk、hw1_clk、hw2_clk、hw3_clk。 我们完全可以通过名字，抽象这7个clock，进行开/关、rate调整等操作。但这样做有一个缺点：不能很好的处理时钟之间的级联关系，如hw2_clk和hw3_clk都关闭后，pll2_clk才能关闭。因此就引入struct clk结构，以链表的形式维护这种关系。 系统的struct clk是在由clock driver在系统启动时初始化完毕的，我们需要访问某个时钟时，只需要获取它对应的struct clk结构即可，怎么获取呢？通过名字索引就可以。 由于设备(由struct device表示)对应的clock(由struct clk表示)也是固定的啊，可不可以找到设备就能找到clock？可以，不过需要借助device tree。 struct clk定义在drivers/clk/clk.c: struct clk { struct clk_core *core; struct device *dev; // 关联的设备 const char *dev_id; // 来自device->name const char *con_id; // 来自时钟别名 unsigned long min_rate; unsigned long max_rate; unsigned int exclusive_count; struct hlist_node clks_node; // 哈希链表数据节点 }; 2.2 struck clk_core(drivers/clk/clk.c) 
struct clk_core {
const char *name;
const struct clk_ops *ops;
struct clk_hw *hw;
struct module *owner;
struct device *dev;
struct device_node *of_node;
struct clk_core *parent;
struct clk_parent_map *parents;
u8 num_parents;
u8 new_parent_index;
unsigned long rate;
unsigned long req_rate;
unsigned long new_rate;
struct clk_core *new_parent;
struct clk_core *new_child;
unsigned long flags;
bool orphan;
bool rpm_enabled;
unsigned int enable_count;
unsigned int prepare_count;
unsigned int protect_count;
unsigned long min_rate;
unsigned long max_rate;
unsigned long accuracy;
int phase;
struct clk_duty duty;
struct hlist_head children;
struct hlist_node child_node;
struct hlist_head clks; // 哈希双向链表头节点
unsigned int notifier_count;
#ifdef CONFIG_DEBUG_FS
struct dentry *dentry;
struct hlist_node debug_node;
#endif
struct kref ref;
};
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2.3 struct clk_ops(include/linux/clk-provider.h)
struct clk_ops定义在include/linux/clk-provider.h文件中：
/**
* struct clk_ops - Callback operations for hardware clocks; these are to
* be provided by the clock implementation, and will be called by drivers
* through the clk_* api.
*
* @prepare: Prepare the clock for enabling. This must not return until
* the clock is fully prepared, and it's safe to call clk_enable.
* This callback is intended to allow clock implementations to
* do any initialisation that may sleep. Called with
* prepare_lock held.
*
* @unprepare: Release the clock from its prepared state. This will typically
* undo any work done in the @prepare callback. Called with
* prepare_lock held.
*
* @is_prepared: Queries the hardware to determine if the clock is prepared.
* This function is allowed to sleep. Optional, if this op is not
* set then the prepare count will be used.
*
* @unprepare_unused: Unprepare the clock atomically. Only called from
* clk_disable_unused for prepare clocks with special needs.
* Called with prepare mutex held. This function may sleep.
*
* @enable: Enable the clock atomically. This must not return until the
* clock is generating a valid clock signal, usable by consumer
* devices. Called with enable_lock held. This function must not
* sleep.
*
* @disable: Disable the clock atomically. Called with enable_lock held.
* This function must not sleep.
*
* @is_enabled: Queries the hardware to determine if the clock is enabled.
* This function must not sleep. Optional, if this op is not
* set then the enable count will be used.
*
* @disable_unused: Disable the clock atomically. Only called from
* clk_disable_unused for gate clocks with special needs.
* Called with enable_lock held. This function must not
* sleep.
* @save_context: Save the context of the clock in prepration for poweroff.
*
* @restore_context: Restore the context of the clock after a restoration
* of power.
*
* @recalc_rate Recalculate the rate of this clock, by querying hardware. The
* parent rate is an input parameter. It is up to the caller to
* ensure that the prepare_mutex is held across this call.
* Returns the calculated rate. Optional, but recommended - if
* this op is not set then clock rate will be initialized to 0.
*
* @round_rate: Given a target rate as input, returns the closest rate actually
* supported by the clock. The parent rate is an input/output
* parameter.
*
* @determine_rate: Given a target rate as input, returns the closest rate
* actually supported by the clock, and optionally the parent clock
* that should be used to provide the clock rate.
*
* @set_parent: Change the input source of this clock; for clocks with multiple
* possible parents specify a new parent by passing in the index
* as a u8 corresponding to the parent in either the .parent_names
* or .parents arrays. This function in affect translates an
* array index into the value programmed into the hardware.
* Returns 0 on success, -EERROR otherwise.
*
* @get_parent: Queries the hardware to determine the parent of a clock. The
* return value is a u8 which specifies the index corresponding to
* the parent clock. This index can be applied to either the
* .parent_names or .parents arrays. In short, this function
* translates the parent value read from hardware into an array
* index. Currently only called when the clock is initialized by
* __clk_init. This callback is mandatory for clocks with
* multiple parents. It is optional (and unnecessary) for clocks
* with 0 or 1 parents.
*
* @set_rate: Change the rate of this clock. The requested rate is specified
* by the second argument, which should typically be the return
* of .round_rate call. The third argument gives the parent rate
* which is likely helpful for most .set_rate implementation.
* Returns 0 on success, -EERROR otherwise.
*
* @set_rate_and_parent: Change the rate and the parent of this clock. The
* requested rate is specified by the second argument, which
* should typically be the return of .round_rate call. The
* third argument gives the parent rate which is likely helpful
* for most .set_rate_and_parent implementation. The fourth
* argument gives the parent index. This callback is optional (and
* unnecessary) for clocks with 0 or 1 parents as well as
* for clocks that can tolerate switching the rate and the parent
* separately via calls to .set_parent and .set_rate.
* Returns 0 on success, -EERROR otherwise.
*
* @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
* is expressed in ppb (parts per billion). The parent accuracy is
* an input parameter.
* Returns the calculated accuracy. Optional - if this op is not
* set then clock accuracy will be initialized to parent accuracy
* or 0 (perfect clock) if clock has no parent.
*
* @get_phase: Queries the hardware to get the current phase of a clock.
* Returned values are 0-359 degrees on success, negative
* error codes on failure.
*
* @set_phase: Shift the phase this clock signal in degrees specified
* by the second argument. Valid values for degrees are
* 0-359. Return 0 on success, otherwise -EERROR.
*
* @get_duty_cycle: Queries the hardware to get the current duty cycle ratio
* of a clock. Returned values denominator cannot be 0 and must be
* superior or equal to the numerator.
*
* @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
* the numerator (2nd argurment) and denominator (3rd argument).
* Argument must be a valid ratio (denominator > 0
* and >= numerator) Return 0 on success, otherwise -EERROR.
*
* @init: Perform platform-specific initialization magic.
* This is not not used by any of the basic clock types.
* Please consider other ways of solving initialization problems
* before using this callback, as its use is discouraged.
*
* @debug_init: Set up type-specific debugfs entries for this clock. This
* is called once, after the debugfs directory entry for this
* clock has been created. The dentry pointer representing that
* directory is provided as an argument. Called with
* prepare_lock held. Returns 0 on success, -EERROR otherwise.
*
*
* The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
* implementations to split any work between atomic (enable) and sleepable
* (prepare) contexts. If enabling a clock requires code that might sleep,
* this must be done in clk_prepare. Clock enable code that will never be
* called in a sleepable context may be implemented in clk_enable.
*
* Typically, drivers will call clk_prepare when a clock may be needed later
* (eg. when a device is opened), and clk_enable when the clock is actually
* required (eg. from an interrupt). Note that clk_prepare MUST have been
* called before clk_enable.
*/
struct clk_ops {
int (*prepare)(struct clk_hw *hw);
void (*unprepare)(struct clk_hw *hw);
int (*is_prepared)(struct clk_hw *hw);
void (*unprepare_unused)(struct clk_hw *hw);
int (*enable)(struct clk_hw *hw);
void (*disable)(struct clk_hw *hw);
int (*is_enabled)(struct clk_hw *hw);
void (*disable_unused)(struct clk_hw *hw);
int (*save_context)(struct clk_hw *hw);
void (*restore_context)(struct clk_hw *hw);
unsigned long (*recalc_rate)(struct clk_hw *hw,
unsigned long parent_rate);
long (*round_rate)(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate);
int (*determine_rate)(struct clk_hw *hw,
struct clk_rate_request *req);
int (*set_parent)(struct clk_hw *hw, u8 index);
u8 (*get_parent)(struct clk_hw *hw);
int (*set_rate)(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate);
int (*set_rate_and_parent)(struct clk_hw *hw,
unsigned long rate,
unsigned long parent_rate, u8 index);
unsigned long (*recalc_accuracy)(struct clk_hw *hw,
unsigned long parent_accuracy);
int (*get_phase)(struct clk_hw *hw);
int (*set_phase)(struct clk_hw *hw, int degrees);
int (*get_duty_cycle)(struct clk_hw *hw,
struct clk_duty *duty);
int (*set_duty_cycle)(struct clk_hw *hw,
struct clk_duty *duty);
void (*init)(struct clk_hw *hw);
void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
};
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2.4 struct clk_hw(include/linux/clk-provider.h)
/**
* struct clk_hw - handle for traversing from a struct clk to its corresponding
* hardware-specific structure. struct clk_hw should be declared within struct
* clk_foo and then referenced by the struct clk instance that uses struct
* clk_foo's clk_ops
*
* @core: pointer to the struct clk_core instance that points back to this
* struct clk_hw instance
*
* @clk: pointer to the per-user struct clk instance that can be used to call
* into the clk API
*
* @init: pointer to struct clk_init_data that contains the init data shared
* with the common clock framework.
*/
struct clk_hw {
struct clk_core *core;
struct clk *clk; // 由CCF维护，并且提供给用户使用
const struct clk_init_data *init; // 描述该clk的静态属性
};
2.5 struck clk_init_data(include/linux/clk-provider.h)
/**
* struct clk_init_data - holds init data that's common to all clocks and is
* shared between the clock provider and the common clock framework.
*
* @name: clock name
* @ops: operations this clock supports
* @parent_names: array of string names for all possible parents
* @parent_data: array of parent data for all possible parents (when some
* parents are external to the clk controller)
* @parent_hws: array of pointers to all possible parents (when all parents
* are internal to the clk controller)
* @num_parents: number of possible parents
* @flags: framework-level hints and quirks
*/
struct clk_init_data {
const char *name; // 时钟的名字
const struct clk_ops *ops; // 时钟的操作函数
/* Only one of the following three should be assigned */
const char * const *parent_names; // 时钟的父时钟名字列表
const struct clk_parent_data *parent_data; // 时钟的父时钟数据列表
const struct clk_hw **parent_hws; // 时钟的父时钟列表
u8 num_parents; // 父时钟的个数
unsigned long flags;
};
2.6 数据结构之间的关系
为了更加清晰的了解CCF子系统各个数据结构作用和之间的关系，我们绘制其关系图，如下：
不知道你没有发现CCF子系统的数据结构中没有使用设备驱动模型，没包含struct device类型的变量。这应该是clk provider主要为系统提供时钟，而一些系统clk的初始化及使能会早于设备驱动模型的初始化，因此没有使用设备驱动模型，但是还是使用了引用计数功能的。 三、CCF时钟操作API 3.1 获取clock驱动开发人员在进行操作设备的时钟之前，首先需要获取和该时钟关联的struct clk指针，获取的接口如下： struct clk *clk_get(struct device *dev, const char *id); struct clk *devm_clk_get(struct device *dev, const char *id); void clk_put(struct clk *clk); void devm_clk_put(struct device *dev, struct clk *clk); struct clk *clk_get_sys(const char *dev_id, const char *con_id); struct clk *of_clk_get(struct device_node *np, int index); struct clk *of_clk_get_by_name(struct device_node *np, const char *name); struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec);其中clk_get，根据设备指针或者时钟别名参数查找时钟； 如果使用设备树，支持根据设备节点，以及时钟别名（clocks-names属性）获取时钟，需要同时传入dev、con_id; 如果没有指定设备树，支持根据设备名称、时钟别名获取时钟，dev、con_id可以任选一个，或者同时传入； 时钟别名是在时钟初始化的时候调用samsung_clk_register_alias注册的，每个时钟别名对应一个clock lookup，clock lookup中包含了dev_id、con_id、clk、clk_hw等成员。devm_clk_get，和clk_get一样，只是使用了device resource management，可以自动释放； clk_put、devm_clk_put，get的反向操作，一般和对应的get API成对调用； clk_get_sys，类似clk_get，不过使用device的name替代device结构； of_clk_get、of_clk_get_by_name、of_clk_get_from_provider，device tree相关的接口，直接从相应的DTS node中，以index、name等为索引，获取clk； 3.2 clock配置 int clk_prepare(struct clk *clk) void clk_unprepare(struct clk *clk) static inline int clk_enable(struct clk *clk) static inline void clk_disable(struct clk *clk) static inline unsigned long clk_get_rate(struct clk *clk) static inline int clk_set_rate(struct clk *clk, unsigned long rate) static inline long clk_round_rate(struct clk *clk, unsigned long rate) static inline int clk_set_parent(struct clk *clk, struct clk *parent) static inline struct clk *clk_get_parent(struct clk *clk) static inline int clk_prepare_enable(struct clk *clk) static inline void clk_disable_unprepare(struct clk *clk)clk_enable/clk_disable，使能/禁止clock；不会睡眠 clk_prepare/clk_unprepare，使能clock前的准备工作/禁止clock后的善后工作；可能会睡眠 clk_get_rate/clk_set_rate/clk_round_rate，clock频率的获取和设置，其中clk_set_rate可能会不成功(例如没有对应的分频比)，此时会返回错误。如果要确保设置成功，则需要先调用clk_round_rate接口，得到和需要设置的rate比较接近的那个值； clk_set_parent/clk_get_parent设置/获取clock的parent clock； clk_prepare_enable，将clk_prepare和clk_enable组合起来，一起调用； clk_disable_unprepare,将clk_disable和clk_unprepare组合起来，一起调用； prepare/unprepare，enable/disable的说明： 这两套API的本质，是把clock的使能/停止分为atomic和non-atomic两个阶段，以方便实现和调用。因此上面所说的“不会睡眠/可能会睡眠”，有两个角度的含义： 一是告诉底层的clock driver，请把可能引起睡眠的操作，放到prepare/unprepare中实现，一定不能放到enable/disable中； 二是提醒上层使用clock的driver，调用prepare/unprepare接口时可能会睡眠哦，千万不能在atomic上下文(例如中断处理中)调用，而调用enable/disable接口则可放心； 另外，clock的开关为什么需要睡眠呢？这里举个例子，例如enable PLL clk，在启动PLL后，需要等待它稳定。而PLL的稳定时间是很长的，这段时间要把CPU交出(进程睡眠)，不然就会浪费CPU；最后，为什么会有合在一起的clk_prepare_enable/clk_disable_unprepare接口呢？如果调用者能确保是在non-atomic上下文中调用，就可以顺序调用prepare/enable、disable/unprepared，为了简单，framework就帮忙封装了这两个接口。 3.3 clock注册接口 struct clk *clk_register(struct device *dev, struct clk_hw *hw); struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); void clk_unregister(struct clk *clk); void devm_clk_unregister(struct device *dev, struct clk *clk);通过clk_register接口可以将时钟struck clk_hw注册到内核，内核代码会将他们 转换为struct clk，并以树的形式组织在一起。 根据时钟种类的不同，CCF子系统将时钟分为fixed rate、gate、devider、mux、fixed factor、composite clock，每一类时钟都有相似的功能、相似的控制方式，因而可以使用相同的逻辑，统一处理，这充分体现了面向对象的思想。 3.3.1 fixed rate clock这一类时钟具有固定的频率，不能开关、不能调整频率、不能选择parent、不需要提供任何的clk_ops回调函数，是最简单的一类时钟、 在include/linux/clk-provider.h文件中定义struct clk_fixed_rate结构抽象这一类clock，另外提供了一些接口，可以直接注册fixed rate clock，如下： /* * DOC: Basic clock implementations common to many platforms * * Each basic clock hardware type is comprised of a structure describing the * clock hardware, implementations of the relevant callbacks in struct clk_ops, * unique flags for that hardware type, a registration function and an * alternative macro for static initialization */ /** * struct clk_fixed_rate - fixed-rate clock * @hw: handle between common and hardware-specific interfaces * @fixed_rate: constant frequency of clock */ struct clk_fixed_rate { struct clk_hw hw; unsigned long fixed_rate; unsigned long fixed_accuracy; }; #define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw) extern const struct clk_ops clk_fixed_rate_ops; struct clk *clk_register_fixed_rate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned long fixed_rate); struct clk_hw *clk_hw_register_fixed_rate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned long fixed_rate); struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned long fixed_rate, unsigned long fixed_accuracy); void clk_unregister_fixed_rate(struct clk *clk); struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned long fixed_rate, unsigned long fixed_accuracy); void clk_hw_unregister_fixed_rate(struct clk_hw *hw); void of_fixed_clk_setup(struct device_node *np); 3.3.2 gate clock这一类clock只可开关（会提供.enable/.disable回调），可使用下面接口注册： /** * struct clk_gate - gating clock * * @hw: handle between common and hardware-specific interfaces * @reg: register controlling gate * @bit_idx: single bit controlling gate * @flags: hardware-specific flags * @lock: register lock * * Clock which can gate its output. Implements .enable & .disable * * Flags: * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to * enable the clock. Setting this flag does the opposite: setting the bit * disable the clock and clearing it enables the clock * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit * of this register, and mask of gate bits are in higher 16-bit of this * register. While setting the gate bits, higher 16-bit should also be * updated to indicate changing gate bits. * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for * the gate register. Setting this flag makes the register accesses big * endian. */ struct clk_gate { struct clk_hw hw; void __iomem *reg; // 控制该clock开关的寄存器地址（虚拟地址） u8 bit_idx; // 控制clock开关的bit位 u8 flags; spinlock_t *lock; //如果clock开关是独享的，可以使用自旋锁 }; #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) #define CLK_GATE_SET_TO_DISABLE BIT(0) #define CLK_GATE_HIWORD_MASK BIT(1) #define CLK_GATE_BIG_ENDIAN BIT(2) extern const struct clk_ops clk_gate_ops; struct clk *clk_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock); struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock); void clk_unregister_gate(struct clk *clk); void clk_hw_unregister_gate(struct clk_hw *hw); int clk_gate_is_enabled(struct clk_hw *hw); 3.3.3 driver clock这一类clock可以设置分频值（因而会提供.recalc_rate/.set_rate/.round_rate回调），可通过下面接口注册： /** * struct clk_divider - adjustable divider clock * * @hw: handle between common and hardware-specific interfaces * @reg: register containing the divider * @shift: shift to the divider bit field * @width: width of the divider bit field * @table: array of value/divider pairs, last entry should have div = 0 * @lock: register lock * * Clock with an adjustable divider affecting its output frequency. Implements * .recalc_rate, .set_rate and .round_rate * * Flags: * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is * the raw value read from the register, with the value of zero considered * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from * the hardware register * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. * Some hardware implementations gracefully handle this case and allow a * zero divisor by not modifying their input clock * (divide by one / bypass). * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit * of this register, and mask of divider bits are in higher 16-bit of this * register. While setting the divider bits, higher 16-bit should also be * updated to indicate changing divider bits. * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded * to the closest integer instead of the up one. * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should * not be changed by the clock framework. * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED * except when the value read from the register is zero, the divisor is * 2^width of the field. * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used * for the divider register. Setting this flag makes the register accesses * big endian. */ struct clk_divider { struct clk_hw hw; void __iomem *reg; // 控制clock分频比的寄存器地址 u8 shift; // 控制分频比的bit在寄存器的便宜 u8 width; // 控制分频比的bit个数 u8 flags; const struct clk_div_table *table; spinlock_t *lock; }; #define clk_div_mask(width) ((1 |
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