基于Zynq的AXI总线数据传输软件优化 |
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基于 Zynq 的 AXI 总线数据传输软件优化
吴汶泰 ; 詹璨铭
【期刊名称】 《通信技术》
【年 ( 卷 ), 期】 2017(050)007
【摘
要】 Xilinx Zynq-7000 provides a ARM+FPGA monolithic solution quietly suitable for the design of intensive-computing and functionally- embedded system. How to make access to the external interface via various technical approaches and approximate theoretical transmission bandwidth is of great significance. XC7020 is selected as the master chip in typical system application environment, the integrated PS (Processing System) is connected to the PL(Programmable Logic) via AXI bus, while the other peripherals also connected to the PS via the AXI bus. The accessing capability of AXI bus via system function is far from theoretical value, thus the SIMD instruction, DMA technology and Cache technology are used to optimize the software accessing of AXI bus, and the respective test are done for 64~4096 Byte size packages. The test results indicate that the optimized accessing capability is close to the theoretical limit of AXI bus interface.%Xilinx Zynq-7000 提供了一种 ARM+FPGA 单片解决方案 , 非常适合 计算密集、功能丰富的嵌入式系统设计 . 如何通过不同技术路径访问外部接口 , 逼近 理论传输带宽具有重要意义 . 典型系统应用环境中 , 采用 XC7020 作为主控芯片 , 其集 成处理器系统 (Processing System,PS) 通过 AXI 总线与可编程逻辑资源 (Programmable Logic,PL) 相连 , 其他外设也通过 AXI 总线接入 PS. 因为通过系统 |
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