英特尔80186 80188微处理器内部结构及与80C51, |
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CONTENTS PAGE1.0 INTRODUCTION 11.1 System Overview 21.2 Application Examples 2H2.0 OVERVIEW OF THE 80186, 80C51,8052, AND 8044 22.1 The 80186 Internal Architecture 22.2 The MCS-51 Internal Architecture 32.3 The 8044 Internal Architecture 33.0 80186/MICROCONTROLLERINTERACTION 44.0 SYSTEM INTERFACE 54.1 Command/Status Transfers 54.2 Data/Parameter Transfer 54.3 Interrupts 65.0 COMMAND AND STATUS 75.1 Commands 75.1.1 Acknowledging Interrupt 75.1.2 Operations 75.1.3 Illegal Commands 95.2 Status 95.2.1 Interrupt 95.2.2 DMA Operation 95.2.3 Error 95.2.4 Request to Send 95.2.5 Clear to Send 95.2.6 Event 96.0 HARDWARE DESCRIPTION 106.1 Reset 106.2 Sending Commands 106.3 DMA Transfers 116.4 Reading Status 11CONTENTS PAGEH7.0 80186/8044 INTERFACE 127.1 Configuring the 8044 127.2 Transferring a Message with the8044 137.3 Receiving a Message with the8044 137.4 Dumping the 8044 Registers 147.5 Aborting an Operation 147.6 Disabling Transmission orReception 147.7 Handling Interrupts 15CONTENTS PAGE8.0 8044 IN EXPANDED OPERATION 158.1 Transmitting a Message in ExpandedOperation 158.2 Receiving a Message in ExpandedOperation 159.0 CONCLUSION 15APPENDIX A: SOFTWARE A-1
英特尔
80186
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