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1.新建工程     此处型号根据自己板子而定。
   2.新建二输入与非门实体  MYNAND2.vhd文件如下
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MYNAND2 IS
PORT(A,B:IN STD_LOGIC;
Y:OUT STD_LOGIC);
END ENTITY MYNAND2;
ARCHITECTURE ART1 OF MYNAND2 IS
BEGIN
YA1,B=>B1,Y=>Y1);
U2:MYNAND2 PORT MAP(A=>A2,B=>B2,Y=>Y2);
--位置映射
U3:MYNAND2 PORT MAP(A3,B3,Y3);
U4:MYNAND2 PORT MAP(A4,B4,Y4);
END ARCHITECTURE ART2;
4.编写testbench文件 参考链接 点击菜单栏中processing,选择start，选择start testbench template write。此时会自动生成testbench模板到项目文件夹simulation里面，后缀为.vht。在MY74LS00\simulation\modelsim文件夹下。 右键，点setting  点test benches 
 选择…，在文件夹弹窗里面选择刚才的vht文件 点击add，结果如下：  修改名字，和tb文件里面的entity一致  在MY74LS00\simulation\modelsim文件夹下找到MY74LS00.vht文件 testbench文件如下：
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- ***************************************************************************
-- This file contains a Vhdl test bench template that is freely editable to
-- suit user's needs .Comments are provided in each section to help the user
-- fill out necessary details.
-- ***************************************************************************
-- Generated on "05/07/2021 22:28:19"
-- Vhdl Test Bench template for design : MY74LS00
--
-- Simulation tool : ModelSim-Altera (VHDL)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY MY74LS00_vhd_tst IS
END MY74LS00_vhd_tst;
ARCHITECTURE MY74LS00_arch OF MY74LS00_vhd_tst IS
-- constants
constant clk_period :time :=20 ns;
-- signals
SIGNAL A1 : STD_LOGIC;
SIGNAL A2 : STD_LOGIC;
SIGNAL A3 : STD_LOGIC;
SIGNAL A4 : STD_LOGIC;
SIGNAL B1 : STD_LOGIC;
SIGNAL B2 : STD_LOGIC;
SIGNAL B3 : STD_LOGIC;
SIGNAL B4 : STD_LOGIC;
SIGNAL Y1 : STD_LOGIC;
SIGNAL Y2 : STD_LOGIC;
SIGNAL Y3 : STD_LOGIC;
SIGNAL Y4 : STD_LOGIC;
COMPONENT MY74LS00
PORT (
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
Y1 : OUT STD_LOGIC;
Y2 : OUT STD_LOGIC;
Y3 : OUT STD_LOGIC;
Y4 : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
i1 : MY74LS00
PORT MAP (
-- list connections between master ports and signals
A1 => A1,
A2 => A2,
A3 => A3,
A4 => A4,
B1 => B1,
B2 => B2,
B3 => B3,
B4 => B4,
Y1 => Y1,
Y2 => Y2,
Y3 => Y3,
Y4 => Y4
);
init : PROCESS
-- variable declarations
BEGIN
-- code that executes only once
A1 |